Example 8: IP•Tube RS530 at 64 Kbps

Scenario
This sample configuration details an IP•Tube RS530 model which connects to a data encryption device via RS-530. The Ethernet bandwidth must be limited to 64 Kbps due to its path over an ISDN WAN Router connected to a 64Kilobit satellite link. Therefore the user must calculate the desired RS-530 clock rate which will yield a 64 Kbps bandwidth usage on Ethernet, taking into consideration the overhead added with encapsulation of RS-530 data into IP/UDP packets and the ISDN WAN Router's PPP overhead.
For this example, the user will select Frames-Per-Packet = 10. With this TUBE FPP setting, the tables in Chapter 6 indicate an approximate 7% (ratio is 1.069) overhead. The WAN Point to Point Protocol overhead is off set with the Ethernet MAC addresses not being transported accross the WAN link although the HDLC framing does bit stuffing that could bump the data bandwidth by 8%. So the total overhead is 7% for the IP/UDP plus 8% for bit stuffing.
Therefore the desired clock rate on RS530 is 64Kbps/1.15 = 55Kbps. In order to minimize the latency involved in clocking the data from the encryptor's serial interface the encryptor will be clocked at its maximum rate and the Tube Interval setting will be used to hold off clocking the next packet of data until the ISDN WAN router has been able to transmit the prior packet.
To determine the Tube Interval setting take the maximum clocking rate of the DTE divide it by the data rate and subtract one. The Encryptors maximum clocking rate is 2.048Mbps.
Divisor = 2,048,000/55,000 = 37.2.
Round down 2,048,000/37 = 55,351
note: slightly greater clocking rate is ok since bit stuffing of
8% is worst case of every data byte being stuffed.
Interval = Divisor minus 1 = 36
Note: the time of clock gapping equals
((FPP * BytePerFrame* BitsPerByte)/2.048Mbps) times Interval.
FPP = 10; BPP = 64; SCRCLOCK = 55,351; Interval = 36.
(10 * 64*8)/ 2,048,000 * 36 = 0.09 = 90 milliseconds.
This amount of gap can result in synchronization mode limitations. The clock gapping delay can be reduced by reducing the FPP (overheaed impact) and the SCTCLOCK base rate (latency impact) which is set to maximum in this example.